The present invention relates to data processing technology of a multiprocessor configuration, and more particularly to a method and system of performing set-storage-key and insert-storage-key processing for a key storage (hereinafter referred to as "KS"), which stores therein key information concerning a main storage (hereinafter referred to as "MS"), in an information processing system in which a plurality of information processing units have an MS in common.
In an ordinary single-CPU type or multiprocessor type computer system, there is employed a so-called multiprogramming system in which a plurality of programs are processed in a time sharing manner, in order that a plurality of users can employ the same equipment effectively. In the multiprogramming system, different programs use the same main storage, and therefore a storage protection mechanism must be provided to prevent a program from accessing an exclusive region for another program. One approach to providing storage protection is to divide the main storage into several blocks, each of which includes 2 K bytes and is used as the unit of storage protection, and to allot storage keys to the blocks. In this case, each of the programs is given a protection key having the same value as a corresponding storage key. When the program accesses the main storage, the protection key is compared with the storage key. In the case where these keys are identical to each other, or in the case where the protection key is equal to zero, a write operation for a block is allowed. In other cases, however, the write operation is not allowed but an alarm signal is issued. The protection keys are stored in a storage for exclusive use, which is called a key storage (that is, "KS"). Such a storage protection system is disclosed in a Japanese Patent Publication No. 23672/1969 dated Oct. 7, 1969, which is based upon a U.S. Application Ser. No. 334,714 filed on Dec. 31, 1963. In recent computer systems, the key storage stores therein various keys in addition to the protection key. For example, a fetch protection bit is used simultaneously with the storage key. When the fetch protection bit is zero, protection is given only to the write operation. When the fetch protection bit takes the level of "1", protection is given not only to the write operation but also to the fetch operation. Further, a reference bit and a change bit are provided in the key storage.
In order to obtain a high speed information processing system, as regards the MS, the number of banks, each of which forms the operation unit, is increased and the parallel processing capability for the banks is implemented to increase the speed of processing. However, since several kilo-bytes in the MS is provided to correspond to one address in the KS, the multi-bank method in the MS stated above cannot be employed in the KS. Accordingly, the processing for the KS is made at one or one-half machine cycle, to make the processing capability of the KS equivalent to that of the MS.
On the other hand, in a multiprocessor system in which a plurality of processing units hold the MS in common, the MS and KS are theoretically common to all of the processing units, and are therefore required to have a large processing capability. As regards the MS, such a request can be fulfilled by increasing the number of banks and by enhancing the parallel processing for the banks, and as regards the KS, the above request can be accomplished by providing a KS in each processing unit. In this case, theoretically speaking, a key request priority determining unit may be common to the processing units, and this unit will determine the priority among key access requests which are simultaneously generated in the processing units.
For example, in a multiprocessor system which can include four central processing units (hereinafter referred to as "CPU") at the most, it is required to provide in the key request priority determining unit interfaces for CPUs and address sensing circuits, and the number of interfaces and the number of address sending circuits are made equal to the above-mentioned largest number, or four. When the system includes only two CPUs, those interfaces and address sending circuits in the key request priority determining unit which correspond to two CPUs, are not in use. That is, the system lacks the flexibility with respect to the number of CPUs included therein.
Generally speaking, in computer systems including one or more central processing units, when interface circuits with respect to the KS are formed of similar units, some of the interface circuits will not be in use if the number of interface circuits is optimized in a state that the systems include the largest number of central processing units. Therefore, such a system configuration is undesirable from the viewpoint of cost effectiveness. With respect to present day general-purpose large-scale computers, a computer system including two or less central processing units is widely employed, and various interface circuits are optimized, or standardized for such a system configuration. However, it is desired that the interface circuit with respect to the KS is optimized independently of the number of central processing units included in the system.